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Exam Code: DP-203 Practice test 2022 by Killexams.com team
Data Engineering on Microsoft Azure
Microsoft Engineering Practice Test
Killexams : Microsoft Engineering VCE test - BingNews https://killexams.com/pass4sure/exam-detail/DP-203 Search results Killexams : Microsoft Engineering VCE test - BingNews https://killexams.com/pass4sure/exam-detail/DP-203 https://killexams.com/exam_list/Microsoft Killexams : Test Automation Engineer

An exhilarating challenge for a technology expert has become available the most innovative healthcare management company headquartered in South Africa, with an office in San Francisco which has earned a reputation as being a leading disruptor and champion of service excellence over the last decade.

They are looking for a unique talented person that would want to set-up the test automation cycle from the beginning.

  • Bachelor’s Degree a MUST
  • Five years’ experience with automated testing, functional testing, integration testing, regression testing, mobile testing, big data testing, cross platform testing, component testing, security testing, performance testing and UX testing in the healthcare industry
  • Four-year degree relating to computer science/information technology.
  • Familiarity with Agile frameworks and automated testing
  • Cypress test automation testing would be an advantage
  • Previous coding experience with PHP / Python an advantage
  • Proficiency with the following programs is preferred:
    • Atlassian JIRA issue tracking system
    • Atlassian Confluence system
    • Enterprise Architecture Tools
  • Implementation of test automation tools.
  • Develop new test framework, test suites and tools to validate product specific features and use cases
  • Designing and writing test automation scripts
  • Using test automation frameworks
  • Create and develop test scenarios
  • Investigating problems in software as a result of testing
  • Test modifications to products to ensure they are fit for purpose, consistent, and compliant with published standards and guidelines
  • Write test planning documentation from requirements specifications
  • Review all testing documents and other test-related documentation
  • Implement the overall testing strategy
  • Identifying issues, risks and dependencies escalating and managing where appropriate
  • To provide product handovers to both technical and non-technical audiences
  • Provide feedback to developers about automated testing strategies, design fixes, and patches.
  • Perform system load tests for new products.

Desired Skills:

  • Complex Problem Solving
  • Judgment and Decision Making
  • Operations Monitoring
  • Systems Analysis
  • Operations Analysis
  • Quality Control Analysis
  • Critival Thinking

Learn more/Apply for this position

Thu, 17 Nov 2022 10:00:00 -0600 en-US text/html https://it-online.co.za/2022/11/18/test-automation-engineer-10/
Killexams : Advanced Certificate in Bridge Engineering

Resilient infrastructure for stronger communities

Bridge engineers need to be prepared to develop bridges using new construction methods and components, and Boost the seismic resiliency of bridges to combat the problems associated with aging infrastructure. Our online Advanced Certificate in Bridge Engineering prepares students to take on leadership roles in enhancing bridges and infrastructure, making a meaningful impact on communities around the world.

Why Apply?

This certificate is a unique opportunity for practicing civil engineers and working professionals who want to boost their educational credentials and achieve greater success in the field of bridge engineering. It is designed specifically to accommodate a wide range of work schedules.

Curriculum

CIE 579 Bridge and Infrastructure Management and Public Policy is the only required course for the program. 

CIE 579 Bridge and Infrastructure Management and Public Policy covers  the following topics: Roles of bridge engineers in managing highway transportation infrastructure, specificants and standards of practice, capital project development and financing mechanisms, research funding processes, environmental issues, project delivery procurement methods and asset management. 

Elective Courses

Students will complete the 12-credit program with a combination of CIE 579 and any four courses listed below:

Tue, 22 Nov 2022 01:26:00 -0600 en text/html https://www.buffalo.edu/ibe/education/advanced-certificate-in-bridge-engineering.html
Killexams : Software Test Engineer (Simulink) at Datafin Recruitment

ENVIRONMENT:

IF you are seeking a new challenge, an exciting opportunity to launch a career in the Automotive Software arena is open to a Software Test Engineer (Simulink) sought by our client, a provider of cutting-edge Engineering Solutions in Durbanville. Your role will include MATLAB/SIMULINK model-based software development, software verification and automated testing at module-, SIL- and HIL-level as well as developing test scrips for HIL test system. You will require knowledge of J1939 CAN communication and associated test tools/equipment and proficiency in Excel, Word and PowerPoint.

DUTIES:

  • MATLAB/SIMULINK model-based software development.
  • Software verification and automated testing at module-, SIL- and HIL-level.
  • Contribute to Simulink system simulation and plant model development.
  • Requirements management and traceability.
  • Test script development for HIL test system.

REQUIREMENTS:

  • Knowledge of J1939 CAN communication and associated test tools/equipment.
  • Computer literacy (Excel, Word, PowerPoint).

Advantageous –

  • Experience with Simulink Test, Simulink Real Time as well as Polarion ALM tools.

ATTRIBUTES:

  • Attention to detail.
  • Integrity and honesty.
  • Good Written and Verbal Communication (English).
  • Good work ethic.
  • Hardworking, willing to go the extra mile.
  • Professionalism.
  • Work independently.
  • Excellent in task management.
  • Team Player (Work well in a team).
  • Ability to work under pressure and handle priority changes.
  • Have good problem-solving abilities.

While we would really like to respond to every application, should you not be contacted for this position within 10 working days please consider your application unsuccessful.

Desired Skills:

Learn more/Apply for this position

Wed, 23 Nov 2022 10:00:00 -0600 en-US text/html https://it-online.co.za/2022/11/24/software-test-engineer-simulink-at-datafin-recruitment-2/
Killexams : Improving Concurrent Chip Design, Manufacturing, And Test Flows

Semiconductor design, manufacturing, and test are becoming much more tightly integrated as the chip industry seeks to optimize designs using fewer engineers, setting the stage for greater efficiencies and potentially lower chip costs without just relying on economies of scale.

The glue between these various processes is data, and the chip industry is working to weave together various steps throughout these flows by utilizing that data in more places. The goals include better visibility when making tradeoffs in heterogeneous designs, faster time to market, and improved reliability in the field. That will be enabled by in-chip and in-system monitoring capabilities, and bi-directional sharing and utilization of data back and forth across the design-through-manufacturing flow.

“There are almost 23,000 job openings for electrical engineers worldwide,” said Duane Lowenstein, solutions fellow at Keysight. “We don’t produce enough electrical engineers. Are we going to fill that gap in the next 5 or 10 years? Probably not. Part of the reason is what’s called the ‘Grey Tsunami,’ which is that 35% of the population is 65 or older, and it’s growing by 10,000 people a day. We’re not producing 10,000 new people per day to backfill some of these jobs. And even before the pandemic, the average person only spent 4.1 years at a company in the U.S. What does that mean for us as a company? We get a great engineer, we’re excited, and it takes a year to two years to train them to get an understanding our processes. Then they work for us for about a year or two, and they’re gone. This is a big problem.”

It’s also one of the main drivers for increased use of digital twins and related methodologies represents. “Digital twins take work out of the system, and we need to be able to do things today with fewer engineers,” Lowenstein said. “We don’t we have enough people, but even if we did, we would have to change the processes to get that shorter time to market, and to be able to translate that and have repeatability everywhere.”

Alongside of this labor shortage, there are concerns about chip and materials availability and the robustness of the supply chain.

“I can’t go to a single provider and have the issue of that provider experiencing an earthquake or a tsunami or a fire or a pandemic, and suddenly I’m shut down.’ This is exactly what’s happening with the chip manufacturers,” he said. “On top of that, there are capacity constraints, but greater production customization. That means I have to be able to design faster. I have to design more accurately, because that impacts things like yields and predictability. If I can’t build something immediately, and slowly ramp up, that time-to-ramp is a problem because that is a capacity constraint. If I could ramp up in a week versus six months, because my digital twin is exactly what I thought it was going to be, that helps.”

Breaking down silos
In the past, design and test were separate domains. “You designed your product from a functional perspective, and you didn’t even really care what the physical implementation of the product was like,” said Rob Knoth, product management group director in the Digital & Signoff Group at Cadence. “Even that was separate. As design technology evolved, functional design of the product and the physical design of the product started to merge. There was a huge incentive to do that because it shortened time to market and helped reduce margins. In the past 5 to 10 years, test has started to become part of that same conversation.”

It is well accepted that test can no longer be ignored by designers for some key reasons.

“In safety-critical, high-reliability products, you want to make sure that you have zero defects, that you have the long lifetimes expected, and that you’re handling safety in the right ways,” Knoth said. “For these reasons, test increasingly is starting to creep into design planning. That’s coupled with advanced nodes, and making sure that you’re testing for all the new defects on these advanced nodes and keeping an eye on them when they’re in-field. Suddenly, all three parties are sitting at the table with very equal voices. It’s not so much that the designer has to prepare for test, but product design is considering test as one of the three important qualities. You have the end function of your product. You have the physical realization of your product. And you have the test aspects. These are really concurrent activities, as opposed to something that follows along.”

This means the design team needs to keep in mind the physical realities of test — it’s going to consume some area and require routing. And with advanced digital designs, it’s also essential to understand the power, performance, area, and congestion impact of test. At the same time, there are still gaps in how the various pieces intersect, so flows will need to be adjusted as the gaps are filled in.

“There are techniques out there that in some companies are very widely adopted, but are still lagging in things like RTL insertion of test. We see that gaining ground but there’s definitely still places out there that they’re not,” Knoth said.

So just adding DFT, running the test structures in the tester, and getting a pass/fail is not sufficient anymore. “We have much more complexity,” said Richard Oxland, product manager for Tessent Embedded Analytics at Siemens Digital Industries Software. “We’re down at 3nm, so things just got harder. How do we deal with that? Well, we need to throw the kitchen sink at it. But we also cannot massively increase the cost of doing the tests in the tester, along with whatever follow-on costs we get. This means we need to get smarter, as well.”

Especially for the functional verification of safety-critical systems, it’s vital to have test content present in RTL rather than at the gate level. “RTL is what’s being driven with so many of the functional verification simulation jobs being done ahead of physical design, and in parallel, to ensure that you’ve got a working product out,” Knoth noted. “So the more that test is critical to the functioning of the design, the more that test IP has to be present in the files that are being used for functional verification. There’s been a big migration of that content up from the gate level to RTL so that it’s able to be seen by the functional verification.”

Using data differently
This is where digital twins become especially important. A digital twin is a digital representation of a physical thing, which is enabled by doing some kind of sensing and monitoring. “If you don’t have sensing and monitoring capabilities, you can’t have a digital twin,” Oxland said. “You need to have something in there that is reporting important metrics on a regular basis. That’s what helps drive business value.”

Oxland noted that two different types of digital twin applications can be used to drive business value. “One is a closed-loop application, in which you might collect data through the design flow and feed data into a database in the design phase, in the emulation phase, and maybe in the manufacturing phase. Then, in silicon, you’re also feeding data in, and you can correlate how well these correspond to each other as you move down the flows.”

The obvious application for this closed-loop digital twin is to Boost performance, but it may have a significant impact on yield and reliability, as well. “It means you can start to say, ‘I made these design decisions, I tested them in emulation, but in silicon it didn’t work out like I was expecting.’ But you have all the data to be able to close the loop and see the design decision was wrong because, for example, you should have put in an offset of 5nm. This approach is like an extension of Shift Left.”

There are also workflow-style applications that contain the digital twin of the real silicon, for which alerts can be set up. So if is an interconnect latency is greater than 500 milliseconds, for example, it can trigger an alarm indicating there is a problem somewhere in the software stack that needs to be fixed.

What gets monitored on the chip can be classified physically or structurally, such as PVT, then parametrically, with on-chip Agents from proteanTecs. The company leverages what it calls “deep data analytics” based on chip telemetry, using multi-dimensional Agents that operate at both test and in mission-mode. So those agents can monitor performance in real-time and send alerts about degrading performance due to aging and latent defects that were not caught during manufacturing. In addition, the technology can be used for operational, environmental and application monitoring, which measures workload and software stress on the hardware, and for monitoring interconnects in advanced packages. 

“At this level, you may want to detect bus latency,” Oxland said. “If you’re monitoring those things in different levels, you can use them for different purposes. ProteanTecs has a great story about the parametric sensor for aging, which plays into reliability, which then allows you to create the business value in predictive maintenance. So instead of having downtime, you can say, ‘I’m just going to send an engineer out now because looks like in two weeks this chip is going to fail.’ That may save you from violating your SLAs or creating another kind of emergency.”

Embedded analytics are particularly important for examining the interaction between a particular version of software and the design. “We have the ability to see at a more fine-grained level what’s happening, and what the interaction between hardware and software is,” he noted. “Maybe all the tests you run of the software look good. You put it out into the wild, and some end user does something really wacky that causes an issue, but it only occurs once every 100 billion cycles. How are you ever going to detect that? If you have an automatic way of sending an alarm when you’ve got that very long latency detected on a chip, you can fix it. You can send that to the software guys and say, ‘Hey, go check it out.’ In our IP, there are circular buffers, and cross triggering mechanisms that allow you say, ‘This is weird. Next time I see this, I want to be capturing the last 100 cycles, both in this part and in this part.’ That gives you the forensic data.”

Moving into the test space, there are outlier use cases causing problems.

“One of the things that Meta published recently concerns silent data corruption,” Oxland said. “Nobody knows why they’re there or how to find them. However, if you have test structures on the DUT, you can trigger those based on weird events. Maybe you have some point in the day where the chip is not being used as much, and you could take it down, run the test, collect the data, analyze on the chip, or send it up to the cloud and analyze it there. The more you can do on the chip the better. If you’ve got monitors, you can detect issues, and if there’s a structural issue, you can root cause them with a test — and that all can be automated.”

What’s missing
The more physically aware various aspects of test are, the better it dovetails with the design process.

“There’s always going to be room to Boost on this,” said Cadence’s Knoth. “Moving test content to the RTL space sometimes makes that job harder. When you’re inserting something during implementation, it’s very natural and easy to understand, ‘This is test, I can manipulate it differently than the functional circuitry.’ But when you’re inserting stuff at the RTL level, that can be a little trickier. So there’s always going to be room to Boost the implementation flow, the verification, flow, and so on.”

Also, the chip needs to be outfitted with the right kind of sensors to indicate when more tests are needed, or if something needs to be re-tested. For example, maybe the temperature in one part of a chip is high, or a transaction is taking too long.

“We’re still feeling our way into exactly what those kinds of triggers are going to be,” Oxland said. “We need ways to understand all this complexity, and how the tests can be better directed ultimately. We sometimes say, ‘Design for more tests, and design for more than test.’ You have to do a bit of both, somehow — smarter, more comprehensive, cheaper test — but also augmenting test with other types of data, such as PVT, parametric, and functional.”

Some of this has been done for years in markets where reliability is considered critical. “We wanted to know exactly what we were delivering,” said Simon Davidmann, CEO of Imperas. “If there were bits missing, we needed to know. If there were bits that were not the quality we expected, we needed to know. This methodology gave us the ability to choose when we were ready to deliver the product.”

Imperas devised a test-driven design strategy in which tests are implemented concurrently with the work being implemented. “When we’re coming up with a project and writing a specification, we spend a lot of time on planning the testing of it so that we can know when we’re done, which is like hardware design,” Davidmann explained. “We write a test plan as we’re evolving the [processor] model. The person writing the test plan tends to be a different person than the person implementing the model, so there are two people practicing the specification. One is implementing it in a simulator in the model, and the other one is implementing it in a bunch of tests. Sometimes in smaller projects it can be the one person, but often it’s two people. In some projects we use three, with some people that do the coverage on it determining that what we need to ensure is covered. All members of the team take it from the spec. One implements it. One writes the test. One determines how to measure it, because it’s not just code coverage, it’s functional coverage. We use this test-driven methodology so that as we’re evolving the product. We know where we are with it in terms of its quality, and we work at a very detailed level and do white box point tests for every capability and feature.”

To bring these concepts to life requires modeling, and then contrasting that against what’s happening in the real world. “You want the data from real life and want to reflect that back into the digital twin,” said Robert Ruiz, director of product marketing at Synopsys.

Ruiz noted that ATPG tools typically deal with abstractions of design elements by generating some stimulus. “‘Let me check what the output is, and apply that on silicon on the tester.’ That has been okay in years prior, but improving the model requires a deeper dive into this. What’s fairly new as far as real usage we’re seeing in production is to say, ‘Let’s take a look at the SPICE-level netlist, the transistors, and closer to the digital twin concept let’s inject defects. Let’s break open the wires, let’s introduce shorts in some cases. Then, let’s not run the ATPG. Let’s run something closer to the real world, which would be more like a SPICE simulation, and see how it responds.’ And then we reflect that back.”

There are other cases where at-speed test is one of the primary ways to get a high-quality test, which most advanced designs do. If a design is supposed to run at 3 GHz, ideally you want the design to run at 3 GHz internally. The traditional ATPG way is to assume it’s going to run at 3 GHz, then create some type of test. However, the ATPG tool doesn’t really know how to do this, due to the lack of modeling or a connection to a digital twin.

“In latest years, we’ve taken information from a static timing tool, injected that in, and now the ATPG tool says, ‘Based on this information, I know that Path A is a longer path. So I’m going to try to make the test go along this path rather than a shorter path. By doing so, I’m more likely to capture a type of defect, because the longer path is 3 GHz and the shorter path is 2 GHz. Timing models can be improved by looking at the silicon, and path margin monitors can measure the timing of the paths from real silicon. That data could come back to the timing models, and then that information feeds this, and the loop is completed.”

While a number of approaches are available today, they may not be connected with other pieces that could be combined to create a digital twin-type simulation model.

“A lot of this evolves over time,” Davidmann noted. “We developed a methodology for our products. We don’t call it digital twin, but we use simulation, we build other models outside what we do. For example, if we’re working on something quite complicated to do with, for example, cryptography, or DSPs, we will find some encryption algorithm such as in C, use that as our reference, then implement it in the language we’re dealing with. Then, we’ve got a golden reference, which is effectively a simulation digital twin type of context, but very micro-level. It’s exactly the same concept as a digital twin because when we deal with our customers in the RISC-V world, what are they doing? They’re using us as their digital twin. They’ve got the RTL, and they want to know if the RTL does the right thing. It’s a whole verification strategy. Our verification product for RISC-V is like a plug that sits behind their products. When they’ve got a whole simulation in their RTL, they can plug our technology behind it, which has its fingers around it and watches what’s going on. It’s a twin of the complete functionality of a core, configured to be exactly what they’ve got. It sits there monitoring every event, and if it finds things it doesn’t like, it reports it.”

Synopsys’ Ruiz expects that as monitors evolve, they will grab data and Boost models, not just for ATPG, but for design itself. “Better timing models, of course, don’t just benefit ATPG,” he said. “They Boost the ability to put out a design that will meet the performance requirements, along with other improvements for the EDA flow.”

Conclusion
The greatest benefits are seen when these various approaches are tied in with the system deployment, where data is gathered, analyzed, and put to work. There are many moving pieces to this puzzle, and the evolution is complex.

“Digital twin is more a philosophical connection to the solution than anything else,” said Keysight’s Lowenstein. “How do I put it together? How do I change my philosophy toward accepting this, because it’s going to happen?”

He predicts that in 10 years, this will be the primary way chips and systems are developed and tested. “The company that comes up with a very simple way of doing it, with all the connections, is going to make it. It will be very much like an SAP or Oracle implementation. When the idea of these systems came up originally, everyone said it was so complicated, and no one’s ever going to accept this. Now, everybody has an MRP system. It’s going to be the same thing with digital twin-like systems.”


Sun, 27 Nov 2022 18:01:00 -0600 en-US text/html https://semiengineering.com/improving-concurrent-chip-design-manufacturing-and-test-flows/
Killexams : Engineer Shares How to Never 'Go Idle' on Microsoft Teams © Provided by TurboFuture

This is a clever way to outsmart it.

With COVID-19 restrictions dropping across the United States, the debate of whether workers should come back to central offices has returned to the forefront. There are many benefits to letting people work from home, which most workers seem to prefer, while management seems to prefer having direct supervision and control over operations and productivity. Many factors remain in play with there likely to be no consensus decision in the immediate future.

The crux of the argument lies in that control over productivity, along what constitutes as "being productive" as a worker. Remote work often uses communication programs and apps to help teams stay connected and collaborate on projects, but also serve as ways for leadership to monitor their underlings and make sure they are staying focused. There are some ways, as TikTok user @astr0nate shows us, to maintain some autonomy with these oversight attempts. 

View the original article to see embedded media.

Commenters offered some other solutions while expressing their frustration over this onerous mentality. "I start a meeting with myself to see how I look on full screen lol then I end the call. Hope that doesn’t come up in my review lol," replied Baci1437. Nikole Roulhac suggested, "Or just schedule yourself focus time like I do…I could be focusing on work or the back of my eyelids." "Open Microsoft presentation and F5 present. Keeps the green dot alive," noted Smashtops.

Having worked in various remote settings, using these communications apps to spy on workers seems a business necessity but really turns off talent. If these companies cannot adapt their mindsets or loosen the reins, they may lose out on more than just "wasted time."

Mon, 28 Nov 2022 03:38:00 -0600 en-US text/html https://www.msn.com/en-us/news/technology/engineer-shares-how-to-never-go-idle-on-microsoft-teams/ar-AA14EzrP
Killexams : Engineering practice expands in Leeds
Engineering practice expands in Leeds
Martin McGovern and Leah Stuart

A civil, structural and transport engineering practice has doubled the size of its Leeds office to support its expansion plans.

Civic Engineers has moved from a 1,522 sq ft office suite in Tower Works to a 3,163 sq ft building in the Round Foundry, 100 yards away.

In Leeds, the company has worked on the £12m Ironworks project, which has seen land off David Street transformed into 53 apartments, 15 townhouses and two commercial units, just around the corner from the new studio.

The Leeds team has also undertaken extensive strategic planning and placemaking work for Leeds City Council, including Leeds Our Spaces and the Leeds Innovation Arc, and is currently working on the redevelopment of the House of Fraser site in Briggate.

Leah Stuart, director of the Leeds office, said: "As we return to the office, we were really keen to embrace our new studio as a place for collaboration. We recognise the value of coming together as a team, and especially for our younger team members. Giving them the opportunity to learn alongside more experienced engineers helps us all work more effectively.

"We're excited to remain on the South Bank and be part of the Marshalls Mill community. We have worked on the refurbishment of this campus over the years and have seen the progress being made by developers in the surrounding area. It's a fantastic part of the city to be in."

The Leeds studio has grown from five to 16 team members in latest years and the larger office will allow the team to grow further.

Stuart added: "We've got access to a fantastic talent pool here in Leeds and West Yorkshire. We will continue to grow and the new office space will supply us the freedom to expand. The proximity to Leeds Station is a major positive for us.

"Having a nice place to work is essential. We're next to some fantastic local institutions, with loads of cool amenities and that's good for us as a business. We're looking forward to seeing more of the team on a regular basis; sharing ideas and spending time together fuels innovation."

Chris Hartnell, partner at national property consultancy Carter Jonas, said: "We were delighted to help advise Civic Engineers in their search for new offices in Leeds city centre. Their relocation to self-contained offices within the Round Foundry is an endorsement of the South Bank of the city which as seen the latest completion of CEG's Globe Point scheme adjacent."

Mon, 28 Nov 2022 18:05:00 -0600 en text/html https://www.insidermedia.com/news/yorkshire/engineering-practice-expands-relocates-in-leeds
Killexams : Microsoft Pairs with VW to Cure HoloLens Virtual Motion Sickness

While we’ve previously covered the car industry’s plans for applying augmented reality to head-up displays projected onto cars’ windshields, an alternative solution would be for drivers to wear augmented reality glasses like Microsoft’s HoloLens 2.

Volkswagen thought that a great application for the HoloLens 2 was a driving program where drivers on a race track receive steering and braking cues through augmented reality. When VW went to the track to try the system in 2015, however, nothing happened.

It turns out that when the HoloLens 2 goes into a moving vehicle its sensors lose tracking, so the holograms it normally displays disappear. That’s when VW engineers made a call to Microsoft for some very intensive tech support.

Investigation revealed that HoloLens uses two main types of sensors to measure its motion — visible light cameras and an inertial measurement unit. The IMU measures acceleration and rotational speed.

Put this system into a moving car and it suffers the electronic equivalent of motion sickness. That happens when the motion we see is decoupled from the motion we feel, and when a HoloLens goes into a moving vehicle, the very same thing happens as the processor tries to reconcile what it’s seeing through the cameras with the motion its accelerometer detects.

Just as the problem is similar to human motion sickness, so is the solution. Looking out the window to get your bearings is often helpful for preventing motion sickness. For the HoloLens, that means connecting a GPS on the car to the glasses so that they have a firmer understanding of their position compared to their surroundings.

Joshua Elsdon, a Microsoft senior software engineer who worked on the project, had to find solutions from his Zurich apartment during the Covid shutdown. He mocked up a solution using a plastic box, sticking bits of tape inside to add visual texture and supply the HoloLens cameras elements to track.

He rode trams and buses around Zurich wearing a HoloLens headset, making sure its holograms held up as the vehicles moved. At night, Elsdon even rode up and down elevators in his apartment building to keep testing the technology.

“We had to do a lot of testing in my apartment,” Elsdon said. “These aren’t ideal development conditions. All of this stuff was done remotely and distributed across different countries, which was interesting.”

Now VW has a prototype of a system that could aid drivers. “We think mixed reality information is the most intuitive information we could provide to enhance our customers’ user experience,”, said the head of the data science team at Volkswagen Group Innovation, Andro Kleen. “Because what you see there, and what you need to process, is very close to what humans normally see and process. It’s not so abstract.”

Image courtesy of Microsoft Corp.Hololens-2-lifestyle-imagery-male-1024x683.png

HoloLens 2 glasses look like regular glasses, with a few extra features attached.

The company says that it is expecting to use the HoloLens 2 in several primary areas. One is the fairly conventional application of augmented reality for engineers doing prototyping in R&D, where they can do the iterative development of head-up displays and underlying functions or for sensor data for automated driving.

There are also two new use cases for mobile applications of HoloLens technology now that the problem of its motion sickness has been solved. One is to support professional drivers of heavy-duty and transport vehicles. The goal is to help them control technical systems in familiar and comprehensible ways and to drive in complex environments like mines and dirty roads, where the glasses might display hidden road hazards.

Another use is for vehicle passengers, providing seamless user experiences for automated driving and for passenger entertainment by displaying navigation information, enabling gesture control of car functions, or by projecting additional information such as points of interest in the real dimension.

Microsoft has its own applications in mind. One is to provide help to maintenance technicians aboard ships at sea to perform necessary repairs. Previously, they were able to get assistance walking them through the procedures to do work while ships were docked. Now the system can be used on ships at sea.

“The more remote the equipment or machine is, the harder it is to get the expert on site,” says Marc Pollefeys, Microsoft director of science and an expert in 3D computer vision and machine learning who serves as a professor of computer science at ETH Zurich, a public research university. “This feature turned out to be critical to unlock HoloLens 2 for the maritime space.”

So far, HoloLens’ moving platform feature only works on large ships, but Microsoft says it will refine HoloLens 2 for use in elevators, trains, and other moving environments.

Mon, 21 Nov 2022 10:00:00 -0600 en text/html https://www.designnews.com/automotive-engineering/microsoft-pairs-vw-cure-hololens-virtual-motion-sickness
Killexams : Week In Review: Semiconductor Manufacturing, Test

With the European Council’s adoption of its negotiating mandate for the European Chips Act, member states and the Czech Presidency of the Council have reached a critical milestone in supporting Europe’s efforts to advance manufacturing and supply of critical components, while bolstering R&D capacities for development of next-generation semiconductor innovations, according to SEMI.

China has enlisted tech giants Alibaba and Tencent to aid its efforts in designing semiconductor chips, according to the Financial Times. The Chinese government has set up a consortium of companies and research institutes, including the Chinese Academy of Sciences, to create new chip intellectual property.

A meeting of the Asia Pacific Group sub-section of the Trilateral Commission provided insight into the greater regional response to U.S. export controls, according to a report by Nikkei Asia.

The New York Times ran a profile of U.S. Commerce Secretary Gina Raimondo. The department is expected to lead the work of reviewing and approving CHIPS grants, with any award of more than $3B requiring approval by President Biden. The Times called her “the most important phone call in Washington that many chief executives can make.”

Randhir Thakur, senior vice president and president of Intel Foundry Services, will leave the company at the end of Q1 2023, according to numerous reports.

Foxconn is enticing workers to return as Apple faces a supply crunch. Workers have been protesting pay delays and Covid lockdowns.

The Netherlands is in talks with the U.S. government about export restrictions for semiconductor equipment to China. ASML has not held licenses to ship to China since 2018.

Canada launched its Indo-Pacific strategy this week, saying it would tighten foreign investment rules to protect intellectual property and prevent Chinese state-owned enterprises from snapping up critical mineral supplies.

Routing around U.S. Sanctions, Huawei is building a new manufacturing supply chain across China, from Beijing to its home base of Shenzhen, according to Nikkei Asia.

The parent firm of Russia’s Yandex wants to cut ties with the country to shield its new businesses from the fallout of the war in Ukraine, according to the New York Times.

Taiwan’s economy ministry proposed a 25% tax break for technology R&D, seeking measures to retain its leading position in semiconductor manufacturing.

The Center for Strategic and International Studies (CSIS) is offering a webinar on Dec. 6 on how to improve export controls enforcement using data science and AI.

Manufacturing

Cadence and UMC announced that customers are adopting their certified mmWave reference flow. Mutual customer Gear Radio Electronics successfully taped out a low noise amplifier IC on the first pass, leveraging UMC’s 28HPC+ process technology and the Cadence RF solution.

The Samsung Foundry Forum and the Samsung Memory Tech Day are now available on demand.

OpenLight today announced the general availability of its process design kit (PDK). The OpenLight PDK is ready to be used with the Synopsys photonic IC design solution, and includes indium phosphide active optical elements on-chip that can be directly used by Synopsys OptoCompiler and simulated with the Synopsys OptSim photonic simulator.

Metrology

The General Conference on Weights and Measures (CGPM), at its 27th meeting, created new system of units (SI) designations to express the world’s largest and smallest measurements. The standard designations particularly apply to data densities, expanding from yottobytes (1024 B) to RB, ronnabytes (1027 B) and QB, quettabytes (1030 B).


Fig. 1: New SI designations. Source: CGPM

Test

Advantest made several latest announcements including:

Market Research

The SIA and the Boston Consulting Group published a free report entitled, The Growing Challenge of Semiconductor Design Leadership, which identifies key challenges and opportunities for the U.S. semiconductor design sector. The report calls for an investment tax credit for design to complement the tax credit for manufacturing provided by the CHIPS and Science Act.

Global semiconductor equipment billings rose 9% from the Q2 to Q3 of 2022, and 7% year-over-year to US$28.75 billion, according to SEMI’s Worldwide Semiconductor Equipment Market Statistics (WWSEMS) Report. “Semiconductor equipment revenue growth in the third quarter remained in line with positive forecasts for 2022,” said Ajit Manocha, SEMI president and CEO. “The 9% quarter-over-quarter increase in equipment spending for Q3 reflects the semiconductor industry’s determination to bolster fab capacity to support long-term growth and technology innovation.”

Techcet announced that total deposition material revenues, including sputtering targets, ALD/CVD precursors, and metal chemicals, will approach US$3.9 billion in 2022 and over US$4.1 billion in 2023. Metal plating alone is expected to grow from US$1.1B in 2022 to $1.3B by 2026. Growth drivers include increased use of advanced packaging with RDL and copper pillars as well as multilayer BEOL metalization in logic, buried power rails and backside copper distribution. Techcet forecasts a slight slowing in the market for 2023, but overall strong market growth through 2026.

Academic/Government

Arizona State University will be working with higher education institutions in Mexico, along with industry partners, to boost the production of semiconductors in North America. The CHIPS and Science act includes $500 million for international cooperation.

Purdue University and GlobalFoundries announced a new strategic partnership to strengthen and expand collaboration on semiconductor research and education.

A Nature paper describes how vanadium dioxide glass could be used to store memory. Manipulation of structural—rather than electronic—states could provide a path to ultrascaled low-power functional devices, but the electrical control of such states is challenging, according to the authors.

Further reading

Check out our Test, Measurement & Analytics Newsletter for these highlights and more:

Read a special report on semiconductor investments, as well as imec’s prospects for microfluidics, in our Manufacturing, Packaging & Materials newsletter:

Upcoming events:

  • IEEE International Electron Devices Meeting, Dec. 3-7 (San Francisco, CA)
  • Ansys IDEAS Digitial Forum, Dec. 6 (virtual)
  • NeurlPS, Nov. 29-Dec. 9 (New Orleans/Hybrid)
  • RISC-V Summit, Dec. 13-14 (San Jose)
  • Semicon Japan, Dec. 14-16 (Tokyo)
  • Industry Strategy Symposium (ISS 2023), Jan. 8-11, 2023 (Half Moon Bay, CA)
  • First Annual Chiplet Summit, Jan. 24-26, 2023 (San Jose, CA)

Thu, 01 Dec 2022 18:09:00 -0600 en-US text/html https://semiengineering.com/week-in-review-semiconductor-manufacturing-test-7/
Killexams : ‘I always failed in school’: Meet the farmer who became a Microsoft engineer

From studying under lanterns in a remote village to working at Microsoft, Santosh Mishra has come a long way – and he’s raring to do more. Mishra, a software development engineer at Microsoft, opened up about his journey in an interview with Humans of Bombay.

He revealed that growing up, he was called “murkh” (fool) because no matter how hard he tried, he ended up failing in school. “The words and numbers looked like gibberish to me. Everyone would say, ‘Isse kuch nahi hoga’ (he can’t be helped),” Mishra told Humans of Bombay.

Perhaps convinced that his son would not fare well in school, Mishra’s father told him to start learning how to farm when he was in Class 9. The teenager would help out in the family farm during the day and study at night.

“Our village was in a remote area, we hardly had electricity. I’d study under a lantern. I hated it,” he confessed. But Mishra did not supply up studying – a decision that changed the route his life took.

When he was 14, a teacher noticed Mishra’s issues and took extra time to help him. “It was because of him & my hard work that I passed 10th,” he said.

Once he completed 10th grade, everyone around him assumed he would take up farming, but Mishra wanted to study further. He convinced his family to send him to Patna, but the transition from a remote village to a bustling city brought challenges greater than what Mishra had expected.

“In the city, all my dreams came crashing down; city life was difficult. Somehow, I cleared my 12th. After failing my exam, I moved back home & worked in the khet (farm) again,” said Mishra.

Despite working as a farmer, Mishra continued his education on the side through a distance learning course. He then got admission into NIT for a Master’s degree and moved to Tiruchirappalli, where again he had to contend with the challenges that come with living in a city – foremost among them being his inability to converse fluently in English.

“People bullied me for my weak English. But I focused on myself–I read books, watched movies & taught myself English. Life got easier after that, because now, I had the confidence to sit for the interviews,” Mishra revealed.

During campus placements, he was hired but received the lowest package in his batch. Demoralised but undeterred, he continued to work hard until, a year and a half later, he got another job with a massive hike.

Mishra’s success story did not end there, although to him it was a dream come true. Last year, he got a job offer from Microsoft, again with an impressive hike in salary.

“Life got better–I renovated my family home, invested in real estate, and even got 2 of my younger sisters married,” he said.

Mishra ended the interview with some inspiring words. “Aage bahut kuch karunga, kyunki woh kehte hai na, koshish karne walo ki haar nahi hoti (I plan to do a lot more with my life, because those who try never fail),” he said.
Mon, 28 Nov 2022 18:45:00 -0600 en text/html https://www.moneycontrol.com/news/trends/i-always-failed-in-school-meet-the-farmer-who-became-a-microsoft-engineer-9620531.html
Killexams : Best universities in Australia for engineering degrees 2023

Top 8 universities for engineering in Australia 2023

Scroll down for the full list of best universities for engineering in Australia

Engineering is a good degree choice for any student who wishes to understand how the world is designed and is looking to pursue a career in an industry such as construction, business, transport, government and many more.

At Australian universities, engineering students can choose from a range of specialisations including civil engineering, electrical engineering, aerospace engineering and more. Many students will choose to stay on for a postgraduate course in order to further narrow down their speciality before entering the world of work.

Many engineering courses expect students to carry out some work experience, with some including a year in industry as part of their programme.

Below are the best universities in Australia for engineering degrees.


Best universities in the world for engineering degrees
Best universities in Canada for engineering degrees
Best universities for engineering degrees in the UK
Best universities for engineering degrees in the US


At the University of Melbourne, undergraduate students can choose the bachelor of science, design or biomedicine and then select an engineering major.

To become an internationally accredited engineer, students must complete a two-year master of engineering programme in their chosen specialisation.

Engineering specialisations include: biomedical, chemical and biochemical, civil, electrical, energy, mechanical and more.

Students at the University of Melbourne can access the Melbourne Entrepreneurial Centre, which helps students to get business ideas off the ground with a range of masterclasses, workshops and pitch nights.

The Faculty of Engineering is a partner in the AOTULE network, which provides exchange opportunities at a number of engineering schools across Asia and Oceania.

There are seven different engineering schools at the University of Sydney: aerospace, mechanical and mechatronic; biomedical; chemical and biomolecular; civil; computer science; electrical and information engineering; and project management.

Across these schools, both undergraduate and postgraduate courses are available.

The University of Sydney encourages its students to undertake internships and work placements during their degree, assisted by the institution’s network of more than 1,200 industry partners. The department also offers opportunities to study and research abroad, for either a semester or a year.

There are many clubs and societies for engineering students, covering everything from civil engineering to motor sports. Students can also enter themselves into competitions such as the Formula Society of Automotive Engineers Australasia competition, where students design, build and race a car. There’s also a competition in partnership with Dymocks Australia, where undergraduate students create innovative solutions to challenges with the chance of winning $5,000.

UNSW Sydney has eight different schools of engineering: biomedical; chemical, civil and environmental; computer science; electrical and telecommunication; mechanical and manufacturing; minerals and energy resources; and photovoltaic and renewable energy engineering.

Across these schools, more than 20 undergraduate degrees are available.

Most of the bachelor’s degrees in the UNSW Sydney engineering department include 60 days of industry training. The institution also offers a flexible first-year degree programme for those who have yet to decide on a specialism. Alternatively, students who are certain about the branch of engineering they wish to pursue may choose a more focused degree programme.

Among the range of postgraduate courses are ones in environmental engineering, mechanical engineering, telecommunications and civil engineering. During their degree, all postgraduate students are required to complete a thesis based on their individual research interests.

There is a student society for each engineering school, as well as societies for mechatronics, robotics and women in renewable energy.


What can you do with an aerospace engineering degree?
What can you do with a chemical engineering degree?
What can you do with a civil engineering degree?
What can you do with an electrical engineering degree?
What can you do with a general engineering degree?
What can you do with a mechanical engineering degree?


Before joining an engineering course at The University of Queensland, students must complete the compulsory “Get Set Quiz” to gain an idea of what students will need to know before coming to university.

The first year of the undergraduate course is flexible, allowing students to try out courses in all six of the engineering specialisms on offer before choosing an area to focus on.

Alternatively, students can choose to study in their chosen specialism from day one if they wish.

All engineering students must complete 450 hours of engineering professional practice (EPP) and submit five reflections on this time before graduation. These hours are made up of real industrial engineering practice to prepare students for work after university.

Students also have the opportunity to study abroad for a semester or two. The University of Queensland has partnerships with more than 150 universities across 37 countries, so students can choose from a wide variety of cultures.

Engineering-related student societies at the university include Skirts in Engineering, the Australian Computer Society and the prestigious Engineers Australia.

The bachelor of engineering degree at Monash University starts with a common first year, during which students learn the fundamentals of engineering and its role in society.

All first-year students take classes in nine engineering specialisations to help them decide which area to focus on from second year onwards.

The engineering specialisations are: aerospace, biomedical; chemical; civil; electrical and computer systems; environmental; materials; mechanical; robotics and mechatronics and software.

The two-year master in engineering programme can be taken in five different engineering branches: chemical; civil; electrical; mechanical; and materials. All master’s students are expected to complete 12 weeks of CPD such as industry work experience, volunteering, career sessions and field trips.

There are two main campuses as part of Monash University: the Clayton Campus in Melbourne and the School of Engineering in Malaysia. Students at either have the opportunity to travel and experience both.


Top universities in Australia for engineering degrees 2023

Click each institution to view its full World University Rankings 2023 results. 

Thu, 01 Dec 2022 10:00:00 -0600 en text/html https://www.timeshighereducation.com/student/best-universities/best-universities-australia-engineering-degrees
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